C-based DDR Memory Controller Model
Simulation of designs containing DDR memories and DDR memory controllers can be a slow process. Even with special simulation parameters to bypass initialization steps, it can me many tens of microseconds of simulation time before the controller is ready to accept data. For a large design, this can equate to an hour of actual run time that is lost each time the simulation is started. Also, because of their complexity and often the required memory array size, simulation of HDL-based DDRx SDRAM models can be slow and have enormous system memory demands.
Macnica's C-based DDRx memory controller models both the memory and memory controller using C++ via the PLI interface. Although not cycle accurate, it properly models memory bandwidth behavior based on use (row, column, bank addressing / precharge / refresh, etc.). While it is still good to run simulations using the actual Altera controller and DDRx SDRAM model to ensure all corner cases are covered, the majority of system simulation can be done using the C-based model
Features include: TCL based setup; Support for very large memory sizes; configurable rank, bank, row and column size; memory pre-loading