Macnica Americas IP & Design Services

In addition to their distribution business with its first-class field-technical and applications support, Macnica offers and customizes IP for High Speed Networking, Broadcast Video, Wireless, and PCI Express.

Design services in these application areas is also available. A description of the design services available from Macnica Americas can be downloaded [click here].

We also provide design and integration services around embedded wireless applications [click here].

Use the link under Next Steps to request a design services consultation with Macnica Americas.

Video

P/N Description PDF
MAI-10GRTPV

Professional video transport over IP network solutions based around the SMPTE 2022 standard, including SMPTE2022-1/2/5/6/7, Sony NMI, Sony LLVC, ASPEN, TR-03 (SMPTE2110), TR-04, RFC4175, and AES67

Click here for more detailed data on 10GRTP.


Video Analytics Library The video analytics library includes functions for different types of histogram displays plus a video rotate function. This IP is available individually or as a complete library.  
OSD Color Palette

The OSD Color Palette converts 8bpp Avalon Streaming video from a Frame Reader or other component into a 24- or 32-bpp video stream via a programmable color palette.  It is intended to minimize memory requirements and maximize OSD rendering performance in embedded applications.

  Datasheet
GigE Vision

By using our GigE Vision IP, you can transfer input image data which is read from an image sensor or other source to a Gigabit Ethernet network easily and timely in accordance with the GigE Vision protocol. The GigE Vision IP is suitable for various image transfer related applications which make the fullest possible use of Gigabit Ethernet like high resolution machine vision cameras, high frame rate security cameras,  medical imaging systems required high reliability, and more.

 
V-by-One® HS

The V-by-One® HS is a leading-edge high speed interface technology which THine Electronics, Inc. developed and specified for Flat Panel Display markets. Implementing the V-by-One®HS Functional IP on Altera FPGAs that Macnica offers enables the FPGA based V-by-One® HS technology to offer higher frame rates and higher resolutions for FPDs. The IP has 2 kinds, the transmitter IP and the receiver IP. This makes it possible to reduce the cost considerably comparing with the conventional technology like LVDS.

 
2D Graphic controller IP for Altera FPGAs

The 2D Graphic Controller IP can draw multiple graphic images on top of an input image in real time. As a graphic image, both existing bitmap images and drawn images by the IP can be used. You can overlay such graphic images up to 4 layers with alpha blending functionality at any transparency. By using this IP, you can easily achieve various On-Screen-Display solutions like start-up logos, menus, icons, and characters.

 

Click here to request more information.

High Speed Networking

P/N Description PDF
MAI-10GMACLite

Simple to use, light version of a 10Gb Ethernet MAC, perfect for chip-chip or backplane communications. 

Click here for more information

  Datasheet
MAI-FastXAUI

Double-width 10G XAUI soft PCS implementation for 20G, HiGig, RXAUI, other less common interfaces

Click here for more information

  Datasheet
MAI-MDIO

Clause 22, and Clause 45 compliant MDIO slave. Slave can be wrapped for implementation in QSYS based designs.

Click here for more information

MAI-1588

1588 time stamping IP core with support for 1G or 10G Ethernet

Click here for more information

MAI-20G

20G chip-to-chip Ethernet communication module for high-speed data transfer over 3 lanes running at 6.375Gbps. 

Click here for more detailed data on 20G.

  Datasheet

Click here to request more information.

PCI Express

P/N Description PDF
MAI-DRVEXP

DrivExpress™ is a PCI Express driver integration tool.

  Datasheet

Click here for more detailed data and licensing.

Memory and Clocking

P/N Description PDF
MAI-DDR3

C-based DDR3 simulation model with immediate startup, fast simulation time, and unrestricted modeling of large memories

Click here for more detailed data on DDR3

MAI-MMI

An IP block that enables efficient access to DDRx memory for up to 8 bus masters. 

Click here for more detailed data on MMI.

 

Click here to request more information.

For IP by Mpression click here