V-by-One®HS Functional IP
The V-by-One® HS is a leading-edge high speed interface technology which THine Electronics, Inc. developed and specified for Flat Panel Display markets. Implementing the V-by-One®HS Functional IP on Altera FPGAs that Macnica offers enables the FPGA based V-by-One® HS technology to offer higher frame rates and higher resolutions for FPDs. The IP has 2 kinds, the transmitter IP and the receiver IP. This makes it possible to reduce the cost considerably comparing with the conventional technology like LVDS.
- Maximum transfer rate per lane is 4 Gbps. (Depends on the FPGA the IP implemented in.)
- Verified ALTERA FPGAs: Stratix IV/V GX FPGAs, Arria II/V GX FPGAs, Cyclone IV/V GX FPGAs
- Applicable for not only VESA/SMPTE standard video formats but also any user custom formats.
- Flexible multiple lane configurations according to the requirements of the transfer rates.
- Built in Self Test called FieldBETto check the connection between the transmitter IP and the receiver IP.
Recommendation of Pixel Resolution and Number of Lanes
- Encrypted RTL (Verilog-HDL)
- Sample design of the IP implementation for your reference
- Simulation environment (For Modelsim)
- Design manuals (User's manual, Reference manual, Simulation manual)
Please feel free to contact us for other deliverables.
(Grey highlighted area is IP)
FPGA Resources Used
Functional IP(VX1 TX) : V-by-One®HS Functional IP(Transmitter）
Functional IP(VX1 RX) : V-by-One®HS Functional IP(Receiver）
- Circuit resource in the above table are just reference numbers for your estimation. (MAP mode is OFF.)
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