tCAM-IP, Deterministic Packet Match and Filter

 

 

Highlights

  • Constant search latency of 7 clock cycles
  • Up to 400 million searches per second at 400 MHz
  • Up to one million rule entries depending on configuration
  • Selectable key widths of 64, 56, 48, 40, 32, 24, or 16 bits
  • Simple table memory structure and user interface signals
  • Evaluation demos that combine tCAM with TOE and UDP cores

 

 

 

Why Macnica?

  • Rule-table sizing and memory mapping for your target PPS and burst profile
  • Coupling strategies with TOE/UDP and low latency EMAC for clean data paths
  • Demo flows that validate sustained match rates and update timing
  • Hardware and optics recommendations to keep measured latency consistent

 

Macnica workflow diagram

 

 

 

Key Specifications

  • Function: Ternary CAM match and action
  • Throughput: 400 MSPS searching at 400 MHz
  • Latency: 7 clock cycles from request to decision
  • Tables: Up to 1M rules, configurable key widths

 

Typical Applications

  • Packet filtering and ACLs in gateways and recorders
  • Flow classification before or after encryption
  • Deep packet inspection pre-selectors

 

 

 

Resources

 

 

 

 

Get Started

 

Tell us key width, rule count, and target PPS. We will map table memory, timing, and an integration plan with your chosen MAC and transport cores.

 

 

 

 

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