SLVS-EC RX IP
Next generation Sony CMOS image sensor interface
SLVS-EC is Sony’s next-generation, high-speed interface for high-resolution CMOS image sensors.
This standard is tolerant of lane-to-lane skew because of embedded clock technology that simplifies board level design of high-speed and long distance data transmission.
- Compliant with SLVS-EC Specification Version 1.2
- Supports various functions defined by the SLVS-EC Link layer (FPGA dPCS/PMA is used as Physical layer)
- Supports Byte-to-Pixel conversion for various lane-configurations
- Supports Header analysis and Payload error detection
|Number of Lanes||1, 2, 4, 6, 8|
|Baud Grade||1, 2|
|Bit per Pixel||8, 10, 12, 14|
|Dynamic Mode Change||Supported|
|Multiple Stream||If needed|
* The operating frequency may not be achievable depending on the speed grade, numberof lanes, and other factors of the FPGA used. Please contact Macnica sales department for information about limitations.
- Cyclone V GX
- Arria 10 GX
* Please contact your local Macnica sales representative or through contact form for information about other devices.
- Encrypted RTL (Verilog HDL)
- Reference design
- Simulation environment (For ModelSim)
- User's manual, Reference manual
Device Resource Utilization
Resource Utilization in case of 8 LANE Full Configuration
|Items||Cyclone® V GX||Arria® 10 GX|
|w/o ECC||w/ECC||w/o ECC||w/ECC|
|Total block memory bits||4096||13312||2560||11776|
* The above values are estimated resource utilization of the IP and Transceivers; they may vary depending on your system configuration.
Data output from Sony CMOS image sensor via SLVS-EC is received by the FPGA. The FPGA outputs RAW still image to USB3.0 and live video image to HDMI.
In addition to SLVS-EC Rx IP, another Mpression family IP, “HDMI 2.0 Tx IP” is also used in this demonstration.
Please contact your local Macnica sales representative or through contact form for electrical characterization for Intel FPGA devices regarding SLVS-EC specifications.