2. Basic Altera SoC HPS Usage

Name Creating an FPGA design that includes the Hard Processor System

In this vWorkshop you will learn how to integrate the Hard Processor System (HPS) into your FPGA design and select and pin-out HPS peripherals to the system including HPS GPIO and the HPS SDRAM controller. This vWorkshop assumes a basic understanding of FPGAs and is taught with the FPGA/HW designer in mind.

  • Completion of the introductory workshop "homework" or equivalent knowledge demonstrating you can load new software and a new FPGA image to the Macnica Helio Board
What you'll be able to do after
  • Create an FPGA design that includes the HPS (Hard Processor System) using Qsys
  • Connect Qsys peripherals
  • Pin out the HPS
  • Create Quartus project with HPS, GPIO, and pinned out design for Macnica Helio board, compile, run provided software that uses the system
  • Demonstrations
  • Qsys Review
  • HPS Configuration
  • Demonstration of HPS Pin Muxing Spreadsheet
  • Quartus Assignments
  • System Console
  • Detailed Lab Walk-through
  • Q&A