The Altera Cyclone 10 GX FPGA uses a column I/O structure with 12.5 Gbps transceivers located on the left-hand side of the die. The GPIOs are arranged in vertical columns with 48 I/Os per bank, each with its own high-efficiency memory controller and I/O phase-locked loop (PLL). Additionally, each GPIO bank supports LVDS pairs with a differential input and output buffers, which can be configured for each pair at speeds of up to 1.4 Gbps.
| Product Name | Logic Elements (LE) | Digital Signal Processing (DSP) Blocks | Maximum Embedded Memory | Maximum User I/O Count' | Package Options | |
|
Altera® Cyclone® 10 10CX105 FPGA |
104000 | 125 |
8.439 Mb |
284 | U484, F672, F780 | |
|
Altera® Cyclone® 10 10CX085 FPGA |
85000 | 84 | 6.473 Mb | 216 | U484, F672 | |
|
Altera® Cyclone® 10 10CX150 FPGA |
150000 | 156 | 10.652 Mb | 284 | U484, F672, F780 | |
|
Altera® Cyclone® 10 10CX220 FPGA |
220000 | 192 | 13.43 Mb | 284 | U484, F672, F780 | |