The Altera Cyclone 10 FPGA's sea of gates, which serves as the logic and routing core fabric, is flanked by I/O elements on both sides, with a phase-locked loop (PLL) in each corner. The architecture includes vertical columns of embedded memory blocks (M9K) and 18 x 18 bit multiplier blocks.
In addition, the Altera Cyclone 10 FPGA features highly efficient interconnects and low-skew clock networks that facilitate connectivity between logic structures for clock and data signals.
| Product Name | Logic Elements (LE) | Digital Signal Processing (DSP) Blocks | Maximum Embedded Memory | Maximum User I/O Count' | Package Options | |
|
Altera® Cyclone® 10 10CL006 FPGA |
6000 | 15 |
270 Kb |
176 | U256, E144 | |
|
Altera® Cyclone® 10 10CL010 FPGA |
10000 | 23 | 414 Kb | 176 | M164, U256, E144 | |
|
Altera® Cyclone® 10 10CL016 FPGA |
16000 | 56 | 504 Kb | 340 | M164, U256, U484, E144, F484 | |
| Altera® Cyclone® 10 10CL025 FPGA | 25000 | 66 | 594 Kb | 150 | U256, E144 | |
| Altera® Cyclone® 10 10CL040 FPGA | 40000 | 126 | 1.134 Kb | 325 | U256, E144 | |
| Altera® Cyclone® 10 10CL080 FPGA | 80000 | 244 | 2.745 Kb | 423 | U484, F484, F780 | |
| Altera® Cyclone® 10 10CL120 FPGA | 120000 | 288 | 3.888 Mb | 525 | F484, F780 | |
| Altera® Cyclone® 10 10CL055 FPGA | 55000 | 156 | 2.34 Mb | 321 | U484, F484 | |