Altera Agilex 5 FPGA and SoC Overview

Altera Agilex 5 devices serve a broad range of applications that require high performance, lower power, and smaller form factors. This tier consists of the performance-optimized D-Series FPGAs and the power-optimized E-Series FPGAs. Altera Agilex 5 devices also feature the industry’s first Enhanced DSP with AI Tensor Block, which deliver high-efficiency AI and digital signal processing (DSP) functionality, and the FPGA industry’s first asymmetric applications processor system consisting of dual Arm Cortex-A76 cores and dual Cortex-A55 cores, which enable you to optimize the performance and power efficiency of their workloads. These characteristics make them ideal for midrange FPGA applications across the edge and core including wireless and wireline communications, video and broadcast equipment, industrial applications, test and measurement products, medical electronics, and defense applications.

E-Series FPGAs and SoCs	D-Series FPGAs and SoCs
E-Series FPGAs and SoCs are optimized for power and size— with 50% lower power while delivering up to 2.5X better performance as compared to Cyclone V devices, also with features including transceiver rates up to 24x28 Gbps, PCIe 4.0x4, 6x25GbE, 3,600 Mbps DDR5, dual core of A55 and dual core of A76 make it ideal for intelligent applications at the edge, embedded, and more.	D-Series FPGAs and SoCs are optimized for performance and power efficiency— with 42% lower power while delivering up to 1.5X better performance as compared to Intel Stratix 10 FPGAs, also with features including transceiver rates up to 32x28 Gbps, PCIe 4.0x8, 16x25GbE, 4,000 Mbps DDR5, dual core of A55 and dual core of A76 make it deal for various applications across multiple markets

Altera Agilex® 5 FPGAs and SoCs E-Series Product Table - Device Group A

Altera Agilex® 5 FPGAs and SoCs E-Series Product Table - Device Group B

Altera Agilex® 5 FPGAs and SoCs D-Series Product Table 

Altera Agilex® 5 FPGA Focus Markets

Image Sensor Processing

Inline image processing

• Pixel defect correction
• Vignette correction
• Adaptive noise reduction

Customized Connectivity

• High-definition multimedia interface (HDMI)
• MIPI D-PHY

Hard Processor System

• Flexible embedded software stack
• Graphical user interface

Autonomous Mobile Robots

Flexible I/O

• MIPI
• HDMI
• Time-Sensitive Networking (TSN)
• LVDS

FPGA Acceleration

• Sensor fusion
• Point of cloud processing

Hard Processor System

• RTOS
• Hypervisor functions
• Network features
• User application

Clinical System

Power Optimized

• Low-density option
• Battery-powered clinical equipment

FPGA Acceleration

• Custom image progressing
• AR/VR innovations
• Deterministic low latency

Hard Processor System

• Real-time waveform analysis
• Graphic controls for Human-Machine Interaction (HMI)