Training Schedule

Cytech is pleased to offer FPGA training course in Beijing, Shanghai and Shenzhen office. The Q2 and Q3 training arrangement are below:

TimeLocationEmailTelphone
2013-5-9Shanghaisamhu@cytech.comTel:(021) 6440 1373
2013-7-19BeijingNancyhuang@cytech.comTel:(010) 8260 7990
2013-5-21Shenzhenkarldli@cytech.comTel:(0755) 2693 5811
2013-8-29Shanghaisamhu@cytech.comTel:(021) 6440 1373
2013-10-18BeijingNancyhuang@cytech.comTel:(010) 8260 7990
2013-9-24Shenzhenkarldli@cytech.comTel:(0755) 2693 5811
2013-10-17Shanghaisamhu@cytech.comTel:(021) 6440 1373
2013-11-15BeijingNancyhuang@cytech.comTel:(010) 8260 7990
2013-11-21Shenzhenkarldli@cytech.comTel:(0755) 2693 5811

The course include below modules:

A. Basic CourseB. Optimize CourseC. Application
  • QuartusII design flow
  • Qsys tools
  • New device introduction
  • FPGA timing optimize
  • Coding style and optimize
  • QuartusII advance
  • TSE Design
  • PCI Express design
  • DDR2/3 Interface design

Some course have lab and will use EasyGX dev kit. The training location is Cytech Shanghai, Shenzhen and Beijing training room. The attendee need to bring their own notebook and install related software in advance.

fpga-training-schedule-01
2012 Q3 Timing analysis course in Shanghai
2013 Q1 Design optimize course in Shenzhen
2013 Q1 Design optimize course in Shenzhen

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