AES256-GCM-IP, Authenticated Encryption for 10G and 25G
Line-rate AES-GCM in hardware with 128- or 256-bit keys, 96-bit IV support, and AAD for message integrity.
AES256-GCM-IP provides authenticated encryption for data in motion and high-speed pipelines. The core uses a 128-bit data path and a fully-pipelined architecture so it can sustain 10G and 25G links and scale higher with clock frequency, while producing a 128-bit authentication tag for each packet or record.
Highlights
- AES-GCM with 128- or 256-bit keys
- 96-bit IV handling and standard 128-bit authentication tag
- Additional Authenticated Data input for header integrity
- 128-bit datapath with one block per clock throughput when pipelined
- Parameterizable buffering for burst absorption and long streams
- Clean streaming interfaces for encrypt, decrypt, and tag verify
- Reference designs and test utilities for throughput and NIST vector checks
Why Macnica?
- Packetization and IV management patterns that match your transport stack
- Buffer sizing for jumbo frames and multi-stream operation at 10G and 25G
- Guidance on key rotation and tag verification at the application boundary
- Interoperability with TLS1.3-IP, TOE, UDP, and low-latency EMAC
- Hardware selection for optics and cables that meet your latency and reach
Key Specifications
- Cipher: AES-GCM, 128 or 256-bit key
- IV and tag: 96-bit IV, 128-bit tag, AAD input
- Throughput: 128 bits per clock cycle in pipelined mode, suited to 10G and 25G links
- Interfaces: Streaming payload in and out, register control and status
- Resources: Pure RTL, no CPU or external DDR
Typical Applications
- Secure telemetry and video streams
- Encrypted links between FPGA appliances
- Packet authentication for control and command channels
Resources
Get Started
Tell us link speed, packet sizes, and IV strategy. We will recommend buffer settings, demo projects, and a validated MAC pairing.