UDP10G-IP, 10G UDP Offload

dg-udp dg-udp

Lightweight, full duplex UDP in hardware with very low MAC latency when paired with the low-latency EMAC.

UDP10G-IP constructs and parses UDP frames at line rate with FIFO or streaming interfaces. Combined with the low-latency EMAC, it achieves very short MAC latency and clean timing for vision and low-latency systems.

Highlights

  • Hardware UDP/IP framing and checksum handling
  • FIFO and AXI-Stream options with register control
  • Documented tests for Tx, Rx, and full duplex operation
  • Integrates with 10G and 25G EMAC options
Macnica workflow diagram Macnica workflow diagram

Why Macnica?

  • Latency and jitter budgeting across MAC and UDP for high frame rate sensors
  • Practical buffer guidance that prevents drops during burst and pause conditions
  • Pairing with NVMe-IP for lossless recording and with TLS1.3-IP for secure transport
  • Reproducible demo flows for your specific board and optics
  • Transition support from eval to production, including supply and test fixtures

Key Specifications

  • Ethernet: 10 GbE
  • User interfaces: FIFO or AXI-Stream payload, register control
  • Resources: No external DDR, no CPU in data path

Typical Applications

  • High frame rate cameras and sensors
  • Tick to trade pipelines
  • Edge recorders and telemetry channels

Get Started

Tell us your latency and packet goals. We will map EMAC choice, buffers, and a demo plan.

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