MPression develops technology for the machine vision industry. We strive to provide a superior package of solutions leveraging expertise in key areas such as FPGAs, processors, and interface devices, together with system-level technologies such as power and clock trees. We complete our offerings with expertise in signal integrity, intellectual property, and software support.

While electronic designs are becoming more complex, engineers are required to design products on ever shortening schedules and at lower costs, without compromising performance or quality. Macnica Vision delivers the necessary environment for those engineers to accelerate their electronics designs while maintaining higher quality and performance. We will help you stay one step ahead at the system level.

CMOS Sensor Interface IP Device Package

SLVS-EC v3.0 Rx IP


SLVS-EC v3.0 Rx IP is an interface IP core conceived to run on multiple FPGAs. Using this IP, you can quickly and easily implement products that support the latest SLVS-EC standard v3.0. Our team has also created an evaluation platform to improve your time to market, by providing you with the tools you need to start your development.

  • The FPGAs can receive signals directly from the SLVS-EC Interface.
  • Compatible with the latest SLVS-EC Specification Version 3.0.
  • Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
  • "Evaluation kit”(see below) is available for speedy evaluation at the actual device level.
Example of system configuration using this IP

Example of system configuration using this IP

Overview of SLVS-EC Standard

  • SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-speed & high-resolution image sensors developed by Sony Semiconductor Solutions Corporation.
  • The SLVS-EC standard is standardized by JIIA (Japan Industrial Imaging Association).
slec ec standard


  • SLVS-EC Specification Version 1.2/2.0 and the latest 3.0 are supported.
  • Provides various functions defined in the SLVS-EC Link Layer.
    • Selectable 32 or 64 pixel for output interface
    • Supports 8, 10, 12, 14, 16 bit/pixel
  • Realizes transfer with less overhead compared to conventional ANSI 8b10b by taking advantage of GCC (Gigabit Channel Coding) features added in the latest SLVS-EC Version 3.0.
  • Supports error correction using Error Correction Code (ECC)
  • Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations.
  • Header analysis and payload error detection.
  • Compile options allow removal of unnecessary functions.


SLVS-EC 3.0 specifications

Grade 4: New in SLVS-EC v3.0


*1: Fixed by compiler option
*2: Limited support for Option 2

Scheduled IP release date (by supported FPGA)

Altera® FPGA

  • Arria® 10 FPGA : Scheduled for release in July 2024
  • Agilex™ 7 FPGA : Scheduled for release in July 2024
  • Agilex™ 5 FPGA : Scheduled for release in 2024

For other FPGA families release schedule, please contact us.

Evaluation Kit

SLVS-EC 3.0 evaluation kit

Luminous Card & Sensor


Orders are scheduled to be received in the summer of 2024
* Please contact us for availability details.

Using the evaluation Kit

SLVS-EC 3.0 Connection image

Connection image

SLVS-EC 3.0 External Appearance

External Appearance



Today Sony CMOS image sensors and FPGAs are used in nearly all machine vision cameras, with Sony SLVS-EC, the interface of choice to handle high-speed, long-distance communication. It has become especially popular because it uses an embedded clock technology that’s tolerant of lane-to-lane skew.

Now, with our SLVS-EC Rx IP, Macnica Vision is offering an intellectual property package that makes board-level design for SLVS-EC very easy. It’s the toolkit you need for faster, better, easier and more profitable camera design.


  • Compliant with SLVS-EC Specification Version 1.2/2.0
  • Available both for Intel and Xilinx FPGAs
  • Supports various functions defined by the SLVS-EC Link layer
  • Supports Byte-to-Pixel conversion for various lane-configurations
  • Supports Header analysis and Payload error detection


  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Simulation environment (For ModelSim)
  • User's manual, Reference manual, Simulation manual

Supported Devices

  • Intel Cyclone V GX
  • Intel Cyclone V SX (v1.2)
  • Intel Cyclone 10 GX
  • Intel Arria 10 GX
  • Intel Arria 10 SX (v1.2/2.0)
  • Xilinx Artix-7 (ECC not supported)
  • Xilinx Kintex-7
  • Xilinx Kintex Ultrascale
  • Xilinx Kintex Ultrascale+
  • Microchip PolarFire (Planning)
  • Please contact us about other devices.

SLVS-EC Evaluation Kit

Mpression's new Vision Evaluation Platform can be used to evaluate our SLVS-EC IP in an 8 Lane configuration.


The kit consists of 2 boards: the sensor board based on the IMX537 and the FMC board with two possible connections either through board stacking or with a cable. A CS lens mount and a CS-to-C mount conversion ring are also provided with the kit, enabling you to connect directly your chosen lens for rapid testing.


The FMC board provides the sensor power sequence and can be plugged in directly to an FPGA development board with an FMC connector. For a list of compatible FPGA development boards, please contact us.


  • Customers can create their own custom sensor boards based on our reference design.
  • FMC board compatible with many off the shelf FPGA development boards allowing easy comparison of different sensors.
  • Sensor board provided in CS mount bracket so that it can be compatible with both CS and C (through adapter) lenses for easy and speedy evaluation.
  • Test bed for SLVS-EC and Sony CMOS Image Sensors.

Camera Interface IP Device Packages

GiGE Vision IP

GIGE Vision IP

Now you can develop GigE Vision-compliant products (both 1-gig and 10-gig) much more quickly and economically using this advanced intellectual property package from Macnica Vision. The GigE Vision Device Package includes everything you need to transfer image data from a camera or image sensor to other devices over Gigabit or 10-Gigabit Ethernet networks in real-time. It’s perfect for the design and manufacturing of highly reliable, high-resolution machine vision cameras, medical imaging systems, and other devices.


  • Highly reliable, high-precision image transmission using the GigE Vision and 10GigE Vision protocols
  • 995 Mbps or 9.5 Gbps maximum effective transfer rate
  • Comprehensive reference environment
  • GigE Vision Compliant, certified by the Automated Imaging Association (AIA)
  • Interoperability qualified with various GenICam application vendors
  • Supports IEEE1588 PTP (Precision Time Protocol) as Master and Slave


  • Compliant with GigE Vision Standard Version 1.2/Version 2.0
  • Supports IEEE1588-2008 PTP for 1GigE. (Under development for 10GigE)
  • Compliant with EMVA GenICam Standard Version 2.0
  • Supports Packet Re-transmission
  • Other functions
    • Chunk data transfer, GigE Vision action commands, Timestamp, Packet delay
    • Image data (RGB, YUV, etc.) and RAW data transfer

Supported Devices

  • 1GigE: Intel Cyclone V
  • 10GigE: Intel Cyclone 10 GX


  • Encrypted RTL (Verilog HDL)
  • GigE Vision Device FW Library for Nios II processors
  • Reference environment (sample hardware design, firmware application)
  • User’s manual

CoaxPress IP

CoaxPress 1.1& 2.0 IP

Macnica Vision makes it easy to develop cameras and other devices that will transfer image data from a camera to a PC with a frame grabber via a simple-to-install, 75Ω coaxial cable at up to 6.25 Gbps per lane. CoaXPress, defined by JIIA (the Japan Industrial Imaging Association) is one of the newest and fastest-growing interface standards for machine vision. The CoaXPress 1.1 & 2.0 Device Packages give you everything you need to develop products using the standard, from an encrypted RTL to a software library that will help you support GenICam, the software API for CoaXPress and other machine vision standards.


  • Compliant with CoaXPress Version 1.1.1 and Version 2.0
  • Data transfer rate up to 6.25Gbps/lane (version 1.1.1) / 12.5Gbps/lane (version 2.0)
  • Supports up to 4 Connections
  • Supports up to 4 Streams
  • Supports GenICam
  • Certified and registered under the JIIA Interoperability Test

Supported Devices

  • Cyclone 10 GX
  • Arria 10 GX

* Please contact us about other devices.


  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Firmware for CoaXPress/GenICam including XML generator
  • Documents

Display Interface IP



Enables high speed interface compliant with HDMI 2.0 standard

Bring your HDMI 2.0-compliant products to market quickly and easily using this advanced intellectual property package from Macnica Vision. Our HDMI 2.0 Tx IP / Rx IP package gives you everything you need to provide your products with the transmit/receive functions of the HDMI 2.0 standard using various Intel FPGAs. Depending on the FPGA you use, you’ll be able to transmit and receive 4K and 2K video with up to 24-bit RGB color at up to 60 frames per second, at a maximum transfer rate of 18 Gbps.


  • Enables HDMI 2.0 transmission and reception with the latest Intel FPGAs
  • 18 Gbps maximum transfer rate
  • Supports RGB 24 bit 4k2k@60p transmit and receive
  • Meets all HDMI licensing requirements; compliance confirmed by third-party testing


  • Supports DVI Mode
  • Supports Deep Color (30 bit/36 bit/48 bit) Mode
  • Supports Display Data Channel (DDC), Status and Control Data Channel (SCDC) control
  • Supports Hot Plug Detect, +5V Power Drive control
  • Supports Audio 

Supported Devices

  • Cyclone V GX (Transfer Rate Limited)
  • Cyclone 10 GX
  • Arria V GX (Transfer Rate Limited)
  • Arria 10 GX

Please contact us about other devices.


  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Simulation environment (For ModelSim)
  • User’s manual, Reference manual, Simulation manual

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