SLVS-EC v3.1 RX IP | New High-Speed CMOS Image Sensor Interface
The latest-generation CMOS image sensor interface
SLVS-EC v3.1 RX IP is an interface IP core that runs on Altera® FPGAs. By using this IP core, you can quickly and easily create products that support the latest SLVS-EC standard v3.1. An evaluation kit is also provided for early adoption.
- Realizing receive function from SLVS-EC interface using Altera® FPGA
- Supports the latest SLVS-EC Specification Version 3.1
- Powerful De-Skew function that allows you to design boards without having to worry about skew between lanes.
- "Evaluation kit" (described below) is available for speedy evaluation of actual devices
SLVS-EC Standard Overview
- SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-resolution, high-speed image sensors developed by Sony Semiconductor Solutions Corporation.
- The SLVS-EC standard is being standardized by the Japan Industrial Imaging Association (JIIA).
- For more details, read this.
Features
- Supports SLVS-EC Specification Version 1.2/2.0 and the latest 3.1
- Realizes various functions defined in the SLVS-EC Link layer
- 32 or 64 pixel selectable output interface
- Supports 8, 10, 12, 14, 16 bits per pixel
- By utilizing the features of GCC (Gigabit Channel Coding) added in the latest SLVS-EC Version 3.1, transmission with less overhead compared to conventional ANSI 8b10b is achieved.
- Supports error correction function using ECC (Error Correction Code)
- Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations
- Includes header parsing and payload error detection
- Unnecessary functions can be removed using compile options.
Specifications
| Features | SLVS-EC 3.1 Specifications | Macnica IP Core Supported Specs | |
|---|---|---|---|
Number of Lanes | 1, 2, 4, 6, 8 | YES | |
Baud Rate | Grade 1 (1.152 to 1.25 Gbps) | o | YES |
Grade 2 (2.304 to 2.5 Gbps) | o | YES | |
Grade 3 (4.608 to 5.0 Gbps) | o | YES | |
Grade 4 (9.216 to 10.0 Gbps) | o *1 | YES | |
| Bit per Second | 8, 10, 12, 14, 16 | YES | |
| Packet Footer CRC | o | YES | |
| ECC | Option 1, 2 | Option 1, 2 *2 | |
| Coding | ANSI 8b/10b / GCC | ANSI 8b/10b / GCC | |
*1: Fixed by compiler option
*2: Limited support for Option 2
Supported Devices (Altera FPGAs)
- Arria® 10 FPGA
- Agilex™ 7 FPGA
- Agilex™ 5 FPGA
- Agilex™ 3 FPGA
Evaluation Kit - Macnica "Luminous" Platform
Macnica Luminous Sensor Evaluation Kit comes with a sensor board with an image sensor of choice, C/CS mount lens holder housing, SLVS-EC ribbon cable, and related documentation.
Please contact us for availability.
