What is Sony SLVS-EC Camera Interface?
Sony SLVS-EC: You know when you need it.
Sony’s SLVS-EC Image Sensor Interface (Scalable Low Voltage Signaling with Embedded Clock) has quickly established itself as the future of CMOS Sensor Interfacing, replacing SLVS and subLVDS as the interface of choice for high-end designs. Many Sony sensors support SLVS-EC exclusively, and even other sensor suppliers are starting to adopt this interface as standard.
Why a new interface now?
Currently, the mainstream interface for image sensors is a low-amplitude differential interface called LVDS (Low Voltage Differential Signaling). Because it is resistant to common-mode noise and can transfer data at high speed with low amplitude, it is used in a wide range of applications.
However, as image sensors continue to become faster and higher resolution, there is a growing need to transfer large volumes of image data at even higher speeds and with even lower power consumption. LVDS can send data at about 600 Mbit/sec per differential signal pair (lane), but sensor requirements for connecting to FPGAs are now calling for 8, 16, 32, or even more lanes. LVDS is a widely mastered technology, but connections require precisely suppressing skew across all lanes, and as the number of lanes increases, board design becomes increasingly difficult. As a result, the need to "do something about board design" is only growing stronger.
What is Sony's "SLVS-EC standard"?
The name comes from "Scalable Low Voltage Signaling Embedded Clock." As the name suggests, it is a low-amplitude differential interface similar to LVDS, inheriting the same high noise resistance, but with the major advantages of even lower amplitude, lower power, and an embedded clock.
With LVDS, the clock is sent on a separate lane from the data, which is what makes the board design difficulties mentioned above so pronounced. With SLVS-EC, however, the image sensor side (transmitter) superimposes the clock onto the data for transmission, and the FPGA side (receiver) recovers the clock, making board design easier and enabling data to be sent at higher speed and over longer distances.
Furthermore, in addition to the "physical layer" characteristics described above, Sony has also defined and standardized the "link layer," covering things like initialization and mode switching, as part of the interface for image sensors, making it easier for users to work with.
![]() | SLVS | SubLVDS | |
Effective Data Rate (Baud Grade) | 1: 1.152 to 1.25 Gbps | 594 Mbps | 594 Mbps |
| 2: 2.304 to 2.5 Gbps | |||
| 3: 4.608 to 5.0 Gbps | |||
| 4: 9.216 to 10.0 Gbps | |||
| Line Coding | 8b10b | None | None |
| Lane Configuration | 1, 2, 4, 6, 8 Lanes | 8 Lanes + 1 Clock | 8 Lanes + 1 Clock |
| Clocking Method | Embedded Clock | DDR Source-Synchronous Clock | DDR Source-Synchronous Clock |
| Differential Signal Level | 200mV | 200mV (160mV min) | 150mV (100mV min) |
| Common Signal Level | 200mV | 200mV | 900mV |
| Line Termination (TX) | 2 x 50 Ω Single-end | 2 x 50 Ω Single-end | None |
| Line Termination (RX) | 100 Ω Differential | 100 Ω Differential | 100 Ω Differential |
| Skew Tuning | Do Not Care | Dat /Clock Skew Tuning | Dat /Clock Skew Tuning |
| Supply Voltage | 1.2V | 1.2V | 1.8V |
| Data Format | Byte Packet | Pixel Packet | Pixel Packet |
| H/V Sync | SAV/EAV | SAV/EAV | SAV/EAV |
