The 40Gbps Ethernet IP core solution offers a highly optimized (128-bit datapath) and fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethernet switching applications.

• 40Gbps MAC core
• 40Gbps (40GBase-R) PCS core
• Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
• Statistics counter block (for RMON and MIB)
• MDIO and I2C cores for optical module status and control

• Encrypted MAC and PCS RTL for simulation and synthesis
• Encrypted L2 packet generator and checker RTL for simulation and synthesis
• Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific customizations.
• Technology specific transceiver wrappers for the selected device family
• Source code RTL (Verilog) for AXI4 Lite and Avalon-MM arbiters and address decoders
• Constraint files and synthesis scripts for design compilation
• Linux based APIs/tools to access core configuration and statistics registers
• Design guide(s) and user manual(s)