The Terasic Agilex 7 FPGA Starter Kit leverages the advanced Altera Agilex™ 7 SoC FPGA F-Series devices, providing two options: one with 800K logic elements and another with 2.7M logic elements. With significant improvements over equivalent Stratix® 10 devices, this kit delivers a remarkable 50% higher fabric performance and a 40% lower power consumption.

To meet the needs of compute-intensive applications, the Terasic Agilex 7 FPGA Starter Kit integrates multiple high-end hardware interfaces. These include PCI Express 4.0 x8, a 100G QSFP-28 connector, and an on-board HDMI 2.1 output. The kit ensures optimal acceleration and throughput with up to 16GB of DDR4. Additionally, its on-board FMC+ connector enables extensibility, allowing compatibility with various daughter cards such as Terasic's HDMI-FMC, XTS-FMC, 12G SDI-FMC, and P16E-FMCP daughter card.

Developers can take advantage of the Altera oneAPI and Altera OpenCL support offered by the Agilex 7 FPGA Starter Kit. These frameworks enable effortless customization of unique acceleration workloads, harnessing the full potential of the Altera Agilex™ FPGA present on the kit. By leveraging this kit, electrical engineering professionals can unlock unparalleled performance and efficiency in their FPGA-based projects.

• FPGA: AGFB027R24C2E2V
• Board Size: PCIe Full Height and 3/4 Length
• Onboard USB-Blaster II
• FPGA Boot Configuration: AS x4 (QSPI Flash 2 or 1 Gbit)
• Board Management System
  • Power Monitor
  • Temperature Monitor
  • Auto fan Control

• PCIe Gen4 x8
• HDMI 2.1 Output Port
• DDR4-A: DDR4 SO-DIMM Socket shared with HPS,shipping with 8GB ECC SO-DIMM
• DDR4-B: On-board components 8GB DDR4 with x72 data bus, support ECC (Note )
• One FMC+ connectors with 16 transceivers, supporting VADJ 1.2V
• One QSFP28 Port for 100/40/25/10 GbE network interface
• 2x5 Timing Expansion Header
• User LED x2, Button x2, DIP Switch x2

Note: For AGF 006/008/019/023 device, only support 4GB DDR4 with 40-bit data bus, support ECC

• MicroSD Socket
• DDR4-A: DDR4 SO-DIMM Socket shared with FPGA
• Gigabit Ethernet PHY + RJ45
• UART to USB Port
• LED x1, Button x1, Cold Reset Button

• FPGA Example Code
• Linux BSP
• OpenCL BSP