Low-Latency EMAC, 10G and 25G

Very short MAC latency with lean logic for 10G and 25G Ethernet.

 

The Low-Latency EMAC focuses on minimal Tx and Rx pipeline depth and integrates cleanly with UDP and TCP offload engines. It is available for 10G and for 25G variants that include PCS and RS-FEC when required.

 

 

 

 

Highlights

  • Very short MAC latency at 10G with documented Tx and Rx figures
  • 25G option that integrates EMAC, PCS, and RS-FEC for robust links
  • AXI-Stream or FIFO user interfaces that align with UDP and TCP cores
  • Reference designs and loopback methods for accurate measurement

 

Low-Latency IP block diagram 2

 

 

Why Macnica?

  • MAC selection and transceiver planning for specific Agilex boards and mezzanines
  • End-to-end latency budgeting that includes PHY, MAC, offload core, and user logic
  • Golden tests for loopback, PRBS, and packet timing that your team can repeat
  • Guidance for cabling, optics, and RS-FEC choices to meet link budget and reliability goals
  • Production support for version control and test plans that keep your latency numbers stable across builds

 

Macnica + Toppan

 

 

 

Key Specifications

  • Ethernet: 10 GbE and 25 GbE
  • User interfaces: AXI-Stream or FIFO payload, register control
  • Resources: Compact logic footprint for tight power and area budgets

 

Typical Applications

  • Financial trading and market data
  • Machine vision and robotics
  • Packet capture, timestamping, and test instrumentation

 

 

 

Resources

 

 

 

 

Get Started

 

Share link speed, latency targets, and planned offload cores. We will provide the right EMAC option and a proven reference flow for your board.

 

 

 

 

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