SMPTE ST 2110 IP Core Package

Build broadcast-grade, IP-native products - faster.

Ship ST 2110 products with confidence. Macnica’s SMPTE® ST 2110 FPGA IP Core Package gives you production-proven RTL, SDKs, reference designs, and documentation - everything you need to turn Altera® SoC FPGAs into reliable, standards-compliant media nodes at 10/25/40/100 GbE.

 

Why teams choose Macnica

  • Finish integration faster: Encrypted RTL + simulation models and a complete SDK reduce bring-up time from months to weeks.
  • Design with headroom: Architect for 10/25/40/100 GbE today; scale to 100 GbE workflows when you’re ready.
  • Standards you can trust: Full ST 2110 family (video, audio, ANC), ST 2059 PTP, ST 2022-7 hitless protection, and AMWA NMOS for discovery/connection.
  • Fewer unknowns: Reference designs, implementation guides, and a sample driver/CUI app keep you moving from lab to line.

 

Proven interoperability

JT-NM Tested. Macnica has passed the applicable tests and earned the JT-NM Tested designation, with publicly documented criteria and versions for full transparency.

JT-NM SMPTE ST 2110

 

 

What's inside

Hardware (TX/RX)

  • Encrypted RTL for Quartus & simulation models for Questa
  • License files and implementation guidance

 

Software Development Kit

  • Broadcast Core Engine & Application Library
  • Optional NMOS Adapter Library
  • Sample device driver & CUI application
  • Simulation & software flow guides, user manual, implementation guideline

 

Reference Design

  • Verilog-based hardware reference
  • Step-by-step simulation & bring-up docs

 

Supported standards

  • SMPTE ST 2110: -10 (System/Timing), -20 (Uncompressed Video), -21 (Packet Shaping), -22 (CBR Compressed Video*), -30/-31 (Audio), -40 (ANC)
  • Timing: SMPTE ST 2059-1/-2 (IEEE 1588v2 PTP)
  • Resilience: SMPTE ST 2022-7 (Seamless Protection Switching)
  • Control: AMWA NMOS IS-04 v1.3 (Discovery/Registration), IS-05 v1.1 (Connection)
  • Networking: IGMP v2/v3, SDP parser/generator, in-band control, out-of-band PTP, 10/25/40/100 GbE (ask for 100 G)
  • * JPEG-XS core not included.

 

Ready for your platform

  • Altera Agilex™
  • Stratix® 10 SoC
  • Arria® 10 SoC

 

Built for these products

  • SDI ↔ IP Gateways
  • IP-enabled Broadcast Cameras & Displays
  • Standards Converters, Switchers/Routers
  • Media Servers & Playout Nodes

 

Typical integration flow

  1. Import RTL & license in Quartus; integrate with your own design using Altera Quartus tool per implementation guide.
  2. Simulate with provided models in Questa to verify timing and packetization.
  3. Bring up the reference design on target FPGA; validate PTP & ST 2022-7.
  4. Layer in control with NMOS IS-04/05 adapter.
  5. Customize your app using the Broadcast Core & sample driver/CUI.

 

Get started

 

Talk to a Macnica representative about your bandwidth, format, and NMOS requirements - and ask about our 100 G configurations. We’ll share full deliverables and JT-NM details under NDA as needed.