AB18-PCIeX16

Cross-connect PCIe host and device lanes to build loopbacks and custom topologies for NVMe and PCIe evaluation.

 

AB18-PCIeX16 provides two x16 PCIe sockets with internal TX and RX crossover so you can connect an FPGA board to a PCIe device or to another board. It supports 1, 4, 8, and 16 lane configurations for flexible prototyping.

 

 

 

Highlights

  • Two PCIe x16 sockets with internal crossover routing
  • Supports x1, x4, x8, and x16 link widths
  • Simplifies host to device, device to device, and loopback topologies
  • Useful for NVMe-IP bring up and PCIe path debugging

 

 

 

Why Macnica?

  • We map your desired link width and device path to a stable lab setup
  • Proven loopback and enumeration recipes for Agilex boards
  • Guidance on cables, risers, and fixtures that keep connectors aligned

 

Macnica workflow diagram

 

 

 

Key Specifications

  • Link widths: x1, x4, x8, x16
  • Sockets: Two PCIe x16 connectors with crossed TX and RX pairs
  • Use with: NVMe-IP families, PCIe debugging, device loopbacks

 

Typical Applications

  • PCIe lane bring up and enumeration testing
  • NVMe device evaluation in custom mechanicals
  • Direct device to device experiments

 

 

 

Resources

 

 

 

 

Get Started

 

Share your intended topology and link width. We will provide a wiring map and a loopback test you can run on day one.

 

 

 

 

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