Design Gateway
Overview
Design Gateway delivers hardwired FPGA IP that handles complex protocols without a host CPU or external DDR. The result is simpler designs, lower latency, and better power efficiency. Key domains include NVMe storage, TCP offload, UDP transport, and high-speed Ethernet connectivity for AI, analytics, trading, and industrial networking.
Why Macnica for Design Gateway?
- Faster path to working silicon with Macnica engineering and supply chain support
- Boards, kits, and adapters to bring up NVMe, TCP, and UDP quickly
- Application guidance for Agilex based on proven demos and training material
Core IP & Solutions
- NVMe-IP Host Controller, standalone NVMe host with integrated PCIe bridge and internal buffering, no CPU and no external DDR required. Multi-SSD capable.
- TOE IP, 1G to 200G, TCP Offload in pure logic to avoid high-end CPUs, with Altera reference designs to reduce bring-up time.
- UDP 10G and 25G IP, CPU-less, deterministic transport that pairs with Agilex EMAC hard IP.
- High-Speed Ethernet Connectivity, 100G to 400G paths for node-to-node links in AI and data center networks.
Platform Focus
- Agilex 7, NVMe as external memory for high performance computing, with demo setups using MCIO SSD adapters
- Agilex 5 E-Series, improved TOE10G and UDP10G performance through 10G and 25G EMAC hard IP and Intel 7 efficiency
Industries and Use Cases
AI and accelerated analytics
Move large datasets between accelerators and storage with predictable latency and minimal CPU load. Use TOE100G or TOE200G with UDP100G for transport, pair with NVMe-IP or muNVMe-IP for storage on Agilex 7.
Financial trading and market data
Hit tight-latency targets for order flow, feed handling, and audit logging. Use TOE10G or TOE25G with the Low Latency EMAC, add tCAM-IP for filtering and NVMe-IP for capture, target Agilex 5 for appliances or Agilex 7 for 100G aggregation.
Media, broadcast, and ProAV contribution
Feed encoders and recorders reliably and keep long recordings steady without CPU tuning. Use UDP10G or UDP25G for media streams with TOE10G for control, combine with NVMe-IP for recording on Agilex 5, move to Agilex 7 for 100G hubs.
Industrial vision and robotics
Move high frame rate image data into processing chains with deterministic timing. Use UDP10G or UDP25G with the low-latency EMAC, add NVMe-IP for burst buffers, deploy on Agilex 5 E-Series.
Edge data logging and test instrumentation
Sustain continuous high speed capture in compact enclosures. Use NVMe-IP for steady writes and raNVMe-IP for random access logs, target Agilex 5.
Telecom and 5G core or edge
Scale packet processing and stateful transport while keeping CPU usage low. Use TOE25G or TOE100G with UDP25G or UDP100G, add TLS1.3-IP and AES-GCM for security, select Agilex 7 for core and Agilex 5 for edge.
Smart infrastructure and transportation
Move video and sensor telemetry at the edge with consistent throughput. Use UDP10G or UDP25G with the low-latency EMAC, add NVMe-IP for evidence buffers and AES-GCM for secure transport, target Agilex 5.
Healthcare imaging and medical devices
Move large image streams into processing pipelines and store raw data for review with privacy controls. Use UDP10G or TOE10G for transport and NVMe-IP for capture, add AES-GCM and AES-XTS for protection, select Agilex 5 for devices and Agilex 7 for aggregation.
Aerospace and defense
Meet strict latency and security goals for mission data transport and capture. Use UDP25G or TOE25G for links and NVMe-IP for mission data, add AES-GCM, SHA-256, and tCAM-IP, target Agilex 7.
Cloud and storage appliances
Build NVMe and NVMe over TCP services with stable throughput and low CPU load. Use TOE100G or TOE200G with NVMeTCP-IP for remote targets, pair with NVMe-IP for local pools on Agilex 7.
Product Lineup
- Storage IP
- Networking IP
- Security IP
- Eval Hardware
| Product | Variant | Interface/ Speed | CPU Required | External DDR Required | Key Features | Notable Performance/ Capacity | Altera Support |
|---|---|---|---|---|---|---|---|
| NVMe-IP (Gen5/ Gen4/ Gen3) | Base host controller | PCIe Gen5, Gen4, Gen3 to NVMe SSD | No | No | Standalone NVMe host, built-in PCIe bridge, 256 KB internal buffer, IDENTIFY/ READ/ WRITE/ SMART/ SECURE ERASE/ FLUSH; optional WRITE ZERO, SANITIZE | Sustained > 11 GB/s with PCIe Gen5 SSD (platform dependent) | Agilex 7, Agilex 5 (via networked flows where applicable), Arria 10; see DG docs for board specifics |
| NVMeG4-IP | Soft PCIe Gen4 inside | PCIe Gen4 soft IP + NVMe | No | No | Enables NVMe on devices without Gen4 hard IP, supports multi-SSD RAID topologies | High throughput with low FPGA resource usage | Where Gen4 soft PCIe is applicable |
| raNVMe-IP | Random access optimized | PCIe Gen4/Gen3 to NVMe SSD | No | No | Optimized for random I/O, simple FIFO and register interfaces | > 500 K IOPS random write on high-performance NVMe SSDs | Agilex 7, Arria 10 (per DG docs) |
| muNVMe-IP | Multi-user streaming | PCIe Gen4/Gen3 to NVMe SSD | No | No | Simultaneous multi-user access in hardware | High-throughput concurrent streaming to single NVMe SSD | Agilex family and others per DG docs |
| rmNVMe-IP | Random + multi-user | PCIe Gen4/Gen3 to NVMe SSD | No | No | Combines random access and multi-user features | Parallel read and write by multiple interfaces to one SSD | Agilex family and others per DG docs |
| SATA-IP | Link layer core | SATA III 6 Gbps | No for link, application layer often uses CPU in reference design | Not for link layer core | Implements SATA link (and part of transport), connects to SSD/HDD without external PHY on supported devices | 6 Gbps link layer | Arria 10, Cyclone 10 GX, Arria V, Cyclone V E |
| NVMeTCP-IP | NVMe over TCP host | Up to 100G network path to NVMe-oF storage | No | No | Host-side NVMe/TCP controller in hardware for remote NVMe-oF access | High-performance remote storage access; platform dependent | Agilex and others per DG docs |
| Product | Category | Interface/ Speed | Key Features | Latency/ Throughput | Altera Support |
|---|---|---|---|---|---|
| TOE200G-IP | TCP Offload | 200 GbE | Hardware TCP stack, multi-session (ADV), server and client modes, AXI4-Stream interface | Line rate when paired with appropriate MAC/PHY | Agilex family support via AXI and EMAC integration |
| TOE100G-IP | TCP Offload | 100 GbE | Hardware TCP stack, server and client modes, jumbo frame support | Line rate with DG reference designs | Agilex family support via AXI and EMAC integration |
| TOE25G-IP | TCP Offload | 25 GbE | Hardware TCP, works with DG 10G25G EMAC or 25G EMAC/PCS+RS-FEC | Low-latency with DG EMAC | Agilex and prior Altera families per DG docs |
| TOE10G-IP | TCP Offload | 10 GbE | Hardware TCP, simple data and control interfaces, optional DG low-latency EMAC | Low-latency, full duplex | Agilex 5 and 7 through EMAC integration |
| UDP100G-IP | UDP Offload | 100 GbE | Hardware UDP/IP stack, FIFO data interface, programmable buffers | High throughput at line rate, platform dependent | Agilex 7 F-Series |
| UDP25G-IP | UDP Offload | 25 GbE | Hardware UDP/IP stack, pairs with DG 10G25G EMAC or 25G EMAC/PCS + RS-FEC | Low-latency when used with DG EMAC | Agilex F-Series |
| UDP10G-IP | UDP Offload | 10 GbE | Hardware UDP/IP stack, FIFO data interface, optional DG low latency EMAC | Tx 19.2 ns, Rx 44.8 ns through DG 10G EMAC (MAC latency) | Agilex 7 I-Series, Agilex 5 Sulfur, Arria 10 |
| Low-Latency EMAC 10G/25G | MAC / PCS | 10 GbE, 25 GbE | Low resource MAC; 10G Tx 19.2 ns, Rx 44.8 ns; 25G EMAC/PCS + RS-FEC option | Very-low MAC latency; 25G loopback round-trip ~471 ns | Pairs with UDP/TOE on Agilex |
| Product | Function | Interface/ Speed | Key Features | Typical Use |
|---|---|---|---|---|
| TLS1.3-IP | Transport layer security offload | 1G to 100G | TLS 1.3 handshake and bulk crypto in hardware, integrates with DG networking IP | Industrial IoT, aerospace and defense, secure data in motion |
| AES256-XTS-IP | Block cipher for storage data at rest | Core-specific | AES-256 XTS engine in hardware | Disk and NVMe data at rest encryption |
| AES256-GCM-IP | Authenticated encryption | Core-specific | AES-256 GCM with authentication tag | High speed network payload encryption |
| AES128/256-IP | Block cipher engine | Core-specific | AES-128 and AES-256 modes | Embedded crypto primitives |
| SHA256-IP | Hash function | Core-specific | SHA2/SHA256 hardware hashing | Integrity and authentication |
| tCAM-IP | Ternary CAM | Core-specific | Ternary match for ACLs and filtering | Packet classification, security filtering |
| Product | Category | Interface/ Speed | Capacity/ Ports | Use Case | Other |
|---|---|---|---|---|---|
| AB20-U2PCI | Adapter Board | PCIe x16 to 4x U.2/U.3 NVMe | Up to 4 U.2/U.3 SSDs | NVMe-IP evaluation and prototyping | PCIe Gen5 capable; works with AMD and Altera dev kits |
| AB19-M2PCI | Adapter Board | PCIe to 4x M.2 NVMe | Up to 4 M.2 SSDs | NVMe-IP evaluation and prototyping | PCIe Gen5 capable |
| AB17-M2FMC | Adapter Board | FMC to 2x M.2 NVMe | Up to 2 M.2 SSDs | NVMe-IP bring up on FMC carrier boards | Works with supported FPGA dev kits |
| AB18-PCIeX16 | Adapter Board | PCIe x16 crossover | x16 lane | PCIe crossover for NVMe-IP demos | Used in DG reference designs |
| AB07-USB3FMC-1.8VIF | Adapter Board | USB 3.0 to FMC (1.8V I/O) | Single FMC | General-purpose FMC USB 3.0 interface | I/O voltage 1.8V only |
Get Started
Share your target link speed, packet rate, and SSD count. We will recommend IP cores, a resource estimate, and a demo path on your Agilex platform.
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