Macnica has been developing intellectual property to support the shift from Serial Digital Interface (SDI) to Internet Protocol (IP) based infrastructures since 2011. We successfully demonstrated the first implementation of our SMPTE ST 2022-1/2/5/6 intellectual property at NAB in 2012. We continue to develop highly flexible intellectual property that enables high channel count across multiple types of channels and a mix of standards in support of the Video over IP migration.

Features:

• Support for multiple channels of video, audio, and metadata
• Protocols can be configured on a per-channel basis (mix ST 2110, ST 2022-6)
• ST 2059-1/2 time synchronization
• Integration with SDI interface
• Clock recovery from a video stream or external sync signal

*Macnica’s patented clock recovery methodology allows the video clock to be derived from the packet stream over a wide range of network jitter conditions.

Supported Standards:

• ST 2110-10 (Timing)
• ST 2110-20 (Video Packetization)
• ST 2110-21 (Narrow Sender Traffic Shaping for Uncompressed Video)
• ST 2110-30 (Audio Packetization)
• ST 2110-40 (Metadata Packetization)
• ST 2022-2/6 (1G and 10G Packetization of SDI Streams)
• ST 2022-1/5 (1G and 10G FEC)
• ST 2022-6 (Transport of High Bit Rate Media Signals over IP Networks)
• ST 2022-7 (Seamless Protection Switching)
• ST 2022-8 (SMPTE ST 2022-6 as an essence format within the SVIP system of ST 2110-10)
• ST 2059-1/2 (Time Synchronization)
• NMOS IS-04 (Discovery and Registration)
• NMOS IS-05 (Connection Management)

Macnica’s suite of Video over IP Intellectual Property implements the most up-to-date standards associated with live video transport over IP networks through active participation in the Society of Motion Picture and Television Engineers (SMPTE), Video Services Forum (VSF), Joint Task Force on Networked Media (JT-NM), Alliance for IP Media Solutions (AIMS), and Advanced Media Workflow Association (AMWA) organizations.

JT-NM Tested

Macnica passed all applicable tests in the JT-NM Tested program earning the JT-NM Tested designation. The JT-NM Tested catalogs provide detailed test results and describe all test criteria and methodology as well as listing hardware and software versions of all products tested, offering complete transparency of the entire evaluation process.

Get more details on the JT-NM Tested program and its test results here.

Macnica ST 2110 IP Core

• FPGA IP Core & Reference Design
  • ST 2059/ ST 2110 IP Core (10G - 25G) 
    • Altera Stratix 10 SoC 12G-SDI to 25GbE IP Gateway Reference System
    • Altera Agilex 7 SoC 25GbE Reference System
  • ST 2059/ ST 2110 IP Core (10G)
    • Altera Arria 10 SoC 3G/HD-SDI to 10GbE IP Gateway Reference System
  • ST 2022-6/8 IP Core (10G)
    • Altera Arria 10 SoC 10GbE Reference System

• Software IP for Application Development
  • Device Driver Hardware Access for each of the FPGA design blocks
  • ST 2059 Firmware Protocol Stack
  • ST 2110/ST 2022 SDK
    • ST 2110 Software Suite & Library Suite
    • IGMP Control
    • SDP Management
    • Hardware Control
    • ST 2110 Multi-Application Interface
    • ST 2110 Sample Application
    • ST 2110 Web GUI Application

• AMWA NMOS Software Adaptor
  • Sony NMOS (OSS) and Macnica ST 2110 SDK seamless connection

Deliverables

ST2110 Hardware IP (Tx / Rx)

• Encrypted RTL for Quartus
• Encrypted simulation model for Questa Sim
• License File for Quartus

ST2110 Software Development Kit

• Broadcast Core Engine
• Broadcast Application Library
• NMOS Adapter Library (Optional component)

Documents

• User’s Manual
• Implementation Guideline
  • About Reference design
  • Altera® Core Implementation Guide (XCVR, PLL, etc.)
  • Simulation Guide
  • Software Flow

Reference Design

• HW : Verilog base Reference design
• SW : Sample Device Driver
• SW : Sample CUI Application