QUIC10GC-IP, CPU-Less QUIC Offload for 10G
QUIC10GC-IP combines QUIC transport, TLS 1.3 security, and UDP/IP into one hardware core so your design gets reliable, encrypted networking without a software stack. The core runs the QUIC client, establishes secure sessions, manages multiple streams, and moves payload over a simple streaming interface. It is designed for real-time links that must keep throughput high even on lossy or jittery networks.
Highlights
- QUIC 10 Gbps engine conforming to RFC 9000
- Client-side operation with multiple concurrent streams
- Integrated TLS 1.3 in hardware, including key exchange, session keys, encrypt and decrypt
- Built-in UDP/IP and ARP controllers so no external network stack is required
- Supported cipher suite: TLS_AES_128_GCM_SHA256 with X25519 key exchange and HKDF-SHA256
- Supported signing options for certificates: RSA-PSS-RSAE-SHA256 and ECDSA-P256
- Unaligned Avalon-ST user interface for payload, ring-buffer user memory management
- 32-bit MAC interface via Avalon-ST, nominal 322.266 MHz data clock
- Recommended core clock from 200 MHz, with pipeline designed for sustained 10G operation
- Customizable service options: Stream count, buffer size, certificate size, and 0-RTT session resumption
Why Macnica?
- QUIC design reviews that align stream counts, buffer depth, and link MTU with your latency and throughput goals
- TLS 1.3 certificate planning and integration with your PKI and update processes
- Proven pairing on Agilex with 10G EMAC options, clocking plans, and transceiver settings
- End-to-end flows that combine QUIC with NVMe-IP or NVMeTCP-IP for secure capture, caching, and replay
- Lab-ready validation scripts and packet-loss test profiles so your team can reproduce results quickly
Key Specifications
- Protocol: QUIC client with integrated TLS 1.3, UDP, IP, and ARP
- Line rate: 10 GbE, full-duplex-capable when platform permits
- Cipher suite: TLS_AES_128_GCM_SHA256, X25519, HKDF-SHA256
- Certificates: RSA-PSS-RSAE-SHA256 (2048-bit), ECDSA-P256
- User I/O: Unaligned Avalon-ST for payload, register interface for control and status
- MAC I/F: 32-bit Avalon-ST at 322.266 MHz nominal
- Clocks: Core from 200 MHz recommended
- Memory model: Ring-buffer user memory management
- Collateral: Datasheet, reference design, demo instructions
Typical Applications
- Autonomous systems: Resilient command and telemetry over variable-quality 5G or private wireless
- Medical and industrial links: Authenticated, encrypted streams between edge devices and servers
- Real-time video at the edge: Secure ingestion from cameras and gateways to analysis nodes
- Cloud-native appliances on FPGA: QUIC transport for web-scale backends without a CPU
Resources
Title | Download |
|---|---|
QUIC10GC-IP Core Datasheet |  |
Get Started
Tell us your platform, 10G MAC, stream count, MTU, and loss profile. We will recommend buffer settings, a certificate plan, and a reference design you can validate on your Agilex board.