SLVS-EC v3.0/3.1 RX IP

SLVS-EC v3.0/3.1 RX IP is an interface IP core that runs on Altera® FPGAs. By using this IP core, you can quickly and easily create products that support the latest SLVS-EC standard v3.0. An evaluation kit is also provided for early adoption.

• Realizing receive function from SLVS-EC interface using Altera® FPGA
• Supports the latest SLVS-EC Specification Version 3.0​
• Powerful De-Skew function that allows you to design boards without having to worry about skew between lanes.
• "Evaluation kit" (described below) is available for speedy evaluation of actual devices

• SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-resolution, high-speed image sensors developed by Sony Semiconductor Solutions Corporation.
• The SLVS-EC standard is being standardized by the Japan Industrial Imaging Association (JIIA).

• Supports SLVS-EC Specification Version 1.2/2.0 and the latest 3.0​ and 3.1
• Realizes various functions defined in the SLVS-EC Link layer
  • 32 or 64 pixel selectable output interface
  • Supports 8, 10, 12, 14, 16 bits per pixel
• By utilizing the features of GCC (Gigabit Channel Coding) added in the latest SLVS-EC Version 3.0, transmission with less overhead compared to conventional ANSI 8b10b is achieved.
• Supports error correction function using ECC (Error Correction Code)
• Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations
• Includes header parsing and payload error detection
• Unnecessary functions can be removed using compile options.

*1: Fixed by compiler option

*2: Limited support for Option 2

• Arria® 10 FPGA 
• Agilex™ 7 FPGA 
• Agilex™ 5 FPGA
  

Please contact us for details on availability.